Technical Field
The present application relates to microelectronic assembly and package and more particularly to microelectronic packaging having a redistribution structure.
Description of the Related Art
Multi-die packages and multi-die assemblies which incorporate silicon interposers can be used to provide high speed, high bandwidth or a high degree of parallel interconnections between multiple microelectronic elements, e.g., semiconductor dies, or semiconductor dies having additional wiring thereon, which are arranged side by side above a surface of a common interposer. Silicon interposers are typically formed from a relatively thick wafer in which wiring patterns and contacts are fabricated in a thin layer of the silicon wafer and above the thin layer, after which the bulk of the wafer is ground down or otherwise discarded. As silicon wafers are almost exclusively processed using semiconductor processing equipment in clean rooms, such processing and the discarding of the unneeded bulk wafer can make silicon interposers more expensive and more difficult to fabricate than other types of circuit structures.
In addition, the horizontal area of such multi-die package can be large, and may constrain further miniaturization of a system such as smart phone, tablet, phablet or other handheld device or personal computer in which the multi-chip package is incorporated.
For example, in the prior art multi-chip package 10 seen in FIG. 1, microelectronic elements 11, 12 and 14 overlie and are electrically interconnected with one another by silicon interposer 20 and are electrically interconnected with a substrate 30 through the silicon interposer 20. Electrical coupling of the silicon interposer with an underlying substrate 30 can be provided through electrically conductive features such as vias which formed typically by drilling through multiple levels of contacts and depositing a metal therein such as by electroless or electrolytic plating or, alternatively, physical or chemical vapor deposition processes.
Auxiliary components such as passive components 40, e.g., decoupling capacitors, and/or resistors can be electrically coupled to the substrate 30 outside the horizontal area of the silicon interposer 20, that is, beyond edges 22 of the silicon interposer. Such components 40 can cooperate with the microelectronic elements 11, 12, 14 of the assembly to provide improved function. As further seen in FIG. 1, a thermally conductive element, i.e., a heat spreader 50, can be thermally coupled to rear surfaces 52 of the microelectronic elements. The heat spreader may also serve as a protective cover for the assembly and the components 40 therein.
FIG. 2 further illustrates electrical and mechanical interconnection of the multi-chip package 10 within a system such as described above. For example, the multi-chip package 30 can be mounted on and electrically connected with a circuit panel 60 through solder balls 62. Clamps 70 may engage the package 10 at a foot portion 54 of the heat spreader and an outwardly facing surface 62 of the circuit panel 60. A further component 80 such as a housing, heat sink, cold plate, cooling duct, or fan can be thermally coupled to a surface 56 of the heat spreader which faces away from the microelectronic elements.
Further improvements in the structure and fabrication of a multi-die package or multi-die assembly, as well as the horizontal area occupied thereby, would be desirable.